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Dr. P. Ramanathan

Qualification : Ph.D.

Details of Educational Qualification:

Course Specialization Group College Name/University Year of Passing
Ph.D. Information & Communication Engineering Information & Communication Engineering PSG College of Technology & Anna University, Chennai 2010
M.E. VLSI Design VLSI Design PSG College of Technology & Anna University, Chennai 2006
B.E. Electronics and Instrumentation Electronics and Instrumentation Tamilnadu College of Engineering & Bharathiar University, Coimbatore 1997

Note : Students are advised to meet me in Room No EB-215 F (Staff room) at any time other than my class hours mentioned in the below timetable for any discussions related to the subjects & research.

My Schedule for 2019-20

                                     

List of Publications

S.No Title of the Paper Full Details of Journal Name / Conference Name, Volume number, page number, Date
1 “Power Delay optimized adder for Multiply and Accumulate Units” International Journal of Digital Signal Processing, Vol. 9, Issue 1, pp.11-17.
2 “High Speed Multiplier Design using Decomposition Logic” Serbian Journal of Electrical Engineering, Published by the Faculty of Technical Sciences, Cacak, Serbia, Vol.6, No.1, pp.33-42.
3 “A Novel Power Delay Optimized 32- bit Parallel Prefix Adder for High Speed Computing” International Journal of Recent Trends in Engineering, Academic Publishers, Vol.2, No.1, pp.58-62.
4 “Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product” International Journal of Electronics, Circuits and Systems, Vol.3, No.1, pp.66-70.
5 “Comparative Analysis of Power Delay Product Between Different Families with Achievement of Reduction using Decomposition Algorithm” International Journal of Power, Control, Signal and Computation, Vol.1, No.1, pp.41-46.
6 “Power Estimation of Sequential Circuits using Back Propagation Neural Networks” Emirates Journal for Engineering Research, Published by College of Engineering, United Arab Emirates University,Vol.17, No.2, pp.1-9.
7 “Power Estimation of Benchmark Circuits using Artificial Neural Networks” Pensee Journal, Vo1.75,No.9, pp 427-433.
8 “Area Efficient Carry Select Adder using Negative Edge Triggered Flip-flop” Applied Mechanics and Materials Journal, Trans Tech Publications, Switzerland, Vol. 573, pp 187-193.
9 “Low Power Parallel Prefix Adder” Applied Mechanics and Materials Journal, Trans TechPublications, Switzerland, Vol. 573, pp 194-200.
10 “Low Power High Speed Carry Skip Adder Design using FEYMAN TOFFOLI gate” International Journal of ResearchIn Engineering and Bioscience, Vol.2, Issue No.4, pp 200-208.
11 “Effect of BIRADS Shape Descriptors on Breast Cancer Analysis” International Journal of Medical Engineering and Informatics, Inder Science Publishers, Vol.7 No.1, pp 65-79.
12 “Modified Low Power DADDA Multiplier using Higher Order Compressors” International Journal of Applied Engineering Research, Research India Publications, Vol.10 (9), pp.7287-7291.
13 “High Performance Parallel Prefix Adder for Wider Word Lengths” Global Journal of Pure and Applied Mathematics, Research India Publications,Vol. 11, No.2, pp.733-43.
14 “Synthesis of High Speed Vedic Multiplier” International Journal of Applied Engineering Research, Research India Publications, Vol.10(9), pp. 22614-22617.
15 “Modified Low Power Wallace Tree Multiplier using Higher Order Compressors” International Journal of Electronics Letters, Taylor and Francis Publications, Vol. 5, Issue.2, pp. 177-188.
16 “Modified BLUE Active Queue Management” Advances in Natural andApplied Sciences, Vol. 10(2), pp.29-35.
17 “Implementing Selective Symbolic Execution for Regressive Testing Virtual Prototype” Australian Journal of Basic and Applied Sciences, AENSI Publications, Vol. 10(12), pp. 110-116.
18 “Minimizing the End to End Delay in MANET” Australian Journal of Basic and Applied Sciences, AENSI Publications, Vol. 10(12), pp. 26-34.
19 “Quality-of-Service Diversity based Sub-channel Allocation (QoS-DSCA) for Femtocells in Cellular Network” International Journal of Printing, Packaging and Allied Sciences, Vol. 4 (3) pp. 2095-2109.
20 “Novel Decomposition Algorithm for Power Delay Optimization in Wallace and Carry Save Multipliers” National Journal of Technology, Published by PSG College of Technology, Vol.5, No.4, pp. 92-100.
21 “A novel logarithmic prefix adder with minimized power delay product” Journal of Scientific and Industrial Research, NISCAIR publications, Vol.69, No.1 pp.17-20.
22 "Hybrid Parallel Prefix adder for High Performance Computing” Karpagam Journal of Computer Science, Published by Karpagam University, Vol.4, No.4, pp 1684-1691.
23 “Comparative Analysis and Comparison of various AQM Algorithm for High Speed” Indian Journal of Science and Technology, Vol. 8 (35), pp. 1-12.
24 “Comparative Analysis of Low Power High Performance Flip-Flops in 0.13μm Technology” Proceedings of the 15th International Conference on Advanced Computing and Communication, IIT Guwahati, India, published by IEEE, pp 209-213.
25 “Decomposition Algorithm for Power Delay optimization in Wallace tree Multiplier” Proceedings of the International Conference on Control, Automation, Communication and Energy Conservation (INCACEC 2009), Perundurai, Erode, India, Published by IEEE, pp 1-6.
26 “Power Estimation of Sequential Circuits using Neural Networks” International Conference on Advances in Industrial Engineering Applications (ICAIEA2010), Chennai, India.
27 “New Hybrid Multiplier using Wallace and Dadda Method” International Conference on Computing, Communication and Informatics (ICCCI 2014), Coimbatore, India, Published by IEEE, pp 1-4.
28 “An Efficient GDI based 4 X 4 Vedic Multiplier” International Conference on Innovations in Information, Embedded and Communication Systems (ICIEECS2014), Coimbatore, India, pp 338-344.Papers Published in National Conferences
29 “Hardware Complexity Analysis of Pipelined Array Based FIR filter folding” Proceedings of the third National Conference on Signals Systems and Security (NCSSS 2008), Sathyamangalam.
30 “An Optimized Design of High Performance Hybrid adder using Lings Algorithm” Proceedings of the National Conference on Extreme Engineering and Technological Advancements, Dharmapuri.
31 “Decomposition Algorithm for Power Delay Optimization in Carry Save multipliers” Proceedings of the 1st National Conference on Signal Processing, Communications and VLSI Design Coimbatore.
32 “Comparative Analysis of Power Delay Product Between Different families with achievement of reduction using Decomposition Algorithm” Proceedings of the 1st National Conference on Signal Processing, Communications and VLSI Design, Coimbatore.
33 “Optimization of Power-Delay Product for Arithmetic circuits” Proceedings of the 1st National Conference on Signal Processing, Communications and VLSI Design, Coimbatore.
34 “Design of Low Power Modified Wallace and Dadda Multiplier” TEQIP – II sponsored National Conference on Communication Systems and VLSI Design (NCCSVD 2014), PSG College of Technology, Coimbatore, India.