Dr. Sumit Kale

Qualification : Ph.D.

Details of Educational Qualification:

Course Specialization Group College Name/University Year of Passing
Ph.D. Electronics & Communication Engineering Electronics & Communication Engineering PDPM Indian Institute of Information Technology, Design and Manufacturing, Jabalpur 2017
M.Tech. Microelectronics & VLSI design Electronics & Communication Engineering Shri G S Institute of Technology & Science, Indore 2010
B.E. Electronics & Communication Engineering Electronics & Communication Engineering Samrat Ashok Technological Institute,Vidisha 2006

Note : Students are advised to meet me in Room No : EB-215 D (Staff room) at any time other than my class hours mentioned in the below timetable for any discussions related to the subjects & research.

My Schedule for 2019-20


List of Publications

S.No Title of the Paper Full Details of Journal Name / Conference Name, Volume number, page number, Date
1 Dielectric Modulated Schottky Barrier TFET for the Application as Label-Free Biosensor Silicon, Springer, Dec. 2019. Impact Factor- 1.24
2 Performance Improvement and Analysis of PtSi Schottky Barrier p-MOSFET Based on Charge Plasma Concept for Low Power Applications Silicon, Springer, Apr. 2019. Impact Factor-1.24
3 Charge Plasma Based Source/Drain Engineered Schottky Barrier MOSFET: Ambipolar Suppression and Improvement of the RF Performance Elsevier-Superlattices and Microstructures, Volume 113, January 2018, Pages 799-809
4 Design and Investigation of Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With NiSi Source/Drain IEEE Transactions on Electron Devices, vol. 64, issue 11, pp. 4400-4407, Nov. 2017. Impact Factor - 2.6
5 Ferroelectric Schottky Barrier Tunnel FET with Gate-Drain Underlap : Proposal and Investigation Superlattices and Microstructures, vol. 89, pp. 225-230, 2015.
6 Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering IET Electronics Letters, vol. 51, issue 19, pp. 1536-1538, 2015.
7 Design and investigation of double gate schottky barrier MOSFET using gate engineering IET Micro and Nano Letters, vol. 10, issue 12, pp. 707-711, 2015. Impact Factor - 0.84
8 Ambipolar leakage suppression in Ge n-channel Schottky barrier MOSFETs IETE Journal of Research, vol. 61, issue 4, pp. 323-328, 2015
9 Impact of Underlap Channel on Analog/RF Performance of Dopant Segregated Schottky Barrier MOSFET on Ultra Thin Body SOI IEEE International Conference on Emerging Trends in Engineering, Technology and Science, Thanjavur, Tamilnadu India, 2016.
10 Performance Study of High-k Gate & Spacer Dielectric Dopant Segregated Schottky Barrier SOI MOSFET IEEE 2nd International Conference on Electronics and communication system, pp. 1142-1145, Coimbatore, India, 2015.
11 Influence of Underlap Gate Length on Analog/RF Performance of Pocket Doped Schottky Barrier MOSFET IEEE 2nd International Conference on Electronics and communication system, pp. 1152-1155, Coimbatore, India, 2015
12 Impact of Underlap Channel and Body Thickness on the Performance of DG-MOSFET with Si3N4 spacer IEEE 10th International Conference on Electron Devices and Solid-State Circuits, pp. 1-2, Chengdu, China, 2014
13 A Noble Design of First Order Sigma Delta Modulator International Journal of Electronic and Electrical Engineering, Volume 4, Number 3 , pp. 239-248, 2011, ISSN 0974-2174.
14 Design of CMOS Comparator for Low Power & High Speed International Journal of Electronics & Engineering Research, Vol. 2, No.1, pp. 29 – 34, 2010, ISSN 0975 – 6450
15 Design of Low Power High Speed Comparator for Sigma Delta ADCs National conference in Electrical & Electronics Dept. of SIRT Bhopal on 24th -25th April 2009
  • Two Week Faculty Development Program on Digital VLSI Circuit Design organized by NIT Warangal on 03-12 June 2017.