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Dr. Vikas Vijayvargiya

Qualification : Ph.D.

D.O.J : 16-07-2018

Details of Educational Qualification:

Course Specialization Group College Name/University Year of Passing
Ph.D. Nano-scale Low Power Semiconductor Device and Circuit Design Electronics Engineering Indian Institute of Technology, Indore, India 2016
M.Tech. Microelectronics and VLSI Design Electronics and Communication Engineering SGSITS Indore, India 2009
B.E. Electronics and Instrumentation Engineering Electronics and Instrumentation Engineering IET, DAVV INDORE (M.P.), India. 2006

Note : Students are advised to meet me in Room No EB-301 (Staff Room) at any time other than my class hours mentioned in the below timetable for any discussions related to the subjects & research.

My Schedule for 2019-20

                                     

My Publications

S.No Title of the Paper Full Details of Journal Name / Conference Name, Volume number, page number, Date
1 Effect of drain doping profile on double gate tunnel field effect transistor and its in uence on device RF performance IEEE Transactions on Nanotechnology, vol. 13, no. 5, pp. 974-981.
2 Analog/RF Performance attributes of an underlap tunnel field effect transistor for low power applicationsIET Electronics Letters, vol. 52, no. 7, pp. 559-560.
3 Ultra-Fast current mode sense amplifier for small ICELL SRAM in FinFET with improved offset tolerance, CircuitsSystems and Signal Processing (CSSP), vol.35, no.9, pp.3066-3085.
4 Impact of Device Engineering on Analog/RF Performances of Tunnel Field Effect TransistorJournal of Semiconductor, Science and Technology, IOP journal ,vol.32, no.6. (http://doi.org/10.1088/1361-6641/aa66bd).
5 Dynamic feedback controlled static random access memory for low power applicationsJournal of Low Power Electronics, ASP, ,vol.13, no.1, pp.47-59.
6 Analysis of DC and ana- log/RF performance on Cyl-GAA-TFET using distinct device geometry Journal of Semiconductors,IOP, vol. 38 no.7.
7 Ultra Low Power- High Stability, Positive Feedback Controlled (PFC) 10T SRAM cell for Look up Table (LUT) Design,Integration The VLSI Journal, Science Direct , Accepted.
8 Effect of doping profile on tunneling field effect transistor Proceedings of 9th IEEE Spanish Conference on Electron Devices, Valladolid, Spain, pp. 195-198.
9 Effect of parasitic capacitance on DG HGT- FET and its influence on Device RF Performance Proceedings of 17th InternationalWorkshop on Physics of Semiconductor Devices (IWPSD), Amity University (Noida), India, pp. 757-759.
10 A Non- Volatile Memory MONOS Device for Improved Stability Applications IEEE International Conference on Devices, Circuits and Communications (ICDCCom), BITS Rachi, India pp. 1-3.
11 Data- line Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET 25th Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, PA, USA pp.95-98.
12 Effect of gate and channel engineering on digital performance parameters using tied (3T) and independent (4T) dou- ble gate MOSFETs Proceedings of IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Indore, India pp. 243-247.
13 Investigation of underlap and spacer engineering in multigate-MOSFET for improved short channel characteristics at 14 nm Proceedings of 18th International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India.
14 Investigation of DC Characteristic on DG-Tunnel FET With high-K Dielectric Using Distinct Device Parameter IEEE International Symposium on Nano electronic and Information Systems (iNIS), December 19-21, Gwalior, India, pp. 124-128.
15 A 9T SRAM for ultra low power applications 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 7th-11th Jan 2017, Hyderabad,India.
16 A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy- Efficient SRAM 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 7th-11th Jan 2017, Hyderabad,India.